Advanced Hardware Design for Specialized HPC Postdoctoral Scholar

📁
Postdoctoral Fellow
💼
AM-Applied Math and Computational Sciences
📅
90878 Requisition #

Berkeley Lab’s Computational Research Division has an opening for a Postdoctoral Scholar to evaluate and develop hardware architectural specializations for high performance computing and edge computing applications. 


In the absence of Moore’s Law Scaling, the DOE must investigate alternative paths to continuing computing performance improvements for scientific applications through architectural specialization. Since the beginning of the microchip, we have become accustomed to Moore’s Law relentlessly delivering a doubling of performance, energy efficiency, and density for high-performance computing (HPC) (and all electronic devices) every 18–24 months. This expectation has led to a relatively stable ecosystem built around general-purpose processor technologies such as the x86, ARM, and Power instruction set architectures. However, with the tapering of lithography improvements, shrinking transistors can no longer be relied on exclusively to deliver continued performance improvements in digital electronics. Absent a new transistor technology to replace CMOS, the primary opportunity for continued performance improvement for digital electronics and HPC is to make more efficient use of transistors through architecture specialization, application-specific acceleration, and compilers/programming-models that better control data movement than those available today.   The successful applicant will contribute to the development and evaluation of novel heterogeneous accelerator technologies for extreme heterogeneous SoC (System on Chip) designs, and evaluate their merit for emerging computational workloads for the purpose of maximizing performance and energy efficiency. This work will have broad impact on high performance and other larger-scale computing for critical applications for society and science. 


The successful applicant will need to be familiar with computer architecture and have skills in hardware design in Verilog and use of CAD/EDA tools. It is desirable if the applicant has familiarity with higher-level hardware design languages such as CHISEL, PyRTL, PyMTL or other HDLs. It is also beneficial if the candidate has experience with architectural simulators (GEM5 or FPGA emulation for example).  Using those skills, the successful applicant will design accelerators for computate, memory, or data transfer for key application kernels to demonstrate the merit of this approach. The applicant will also make key intellectual contributions and consequently publish papers to the emerging field of extreme heterogeneous computing and domain-specific specializations. Knowledge of popular HPC applications and FPGA toolflows is a bonus. 


What You Will Do:

  • Based on the needs of the project and in collaboration with the rest of the team:

  • Diagnose performance bottlenecks for scientific codes/kernels on conventional HPC systems by instrumenting those codes/kernels using performance counters and development of microbenchmarks.

  • Identify opportunities for tailored hardware/software design to address those bottlenecks and develop analytic performance models to determine the performance potential for those solutions

  • Design CMOS hardware accelerators for key HPC applications and application kernels.

  • Develop a framework for tightly integrating those accelerators into heterogeneous systems and SoCs that may contain multiple different kinds of accelerator devices.

  • Develop metrics and benchmark tests in order to compare conventional universal programmable processors and enhanced computational accelerators for key HPC applications and algorithms.


What is Required: 

  • PhD or equivalent in a Computing Science or Computer Engineering-related scientific discipline.

  • Knowledge of hardware architecture and system architectures and principles of NoC and SoC design with Arm or RISC-V processing elements.

  • Proficient in Verilog and hardware design in CMOS.

  • Familiarity with hardware CAD tools and evaluation/modelling tools in order to extend existing infrastructure to rapidly evaluate CMOS designs.

  • Demonstrated creativity, initiative and ability to design, develop and implement complex solutions in consultation with designated technical expert(s) and/or supervisor.

  • Experience with writing technical papers and reports.

  • Experience with the use of script languages and system utilities such as configure, Perl, UNIX shell scripts, and “make.”

  • Proven record of working effectively in a team, seeing projects through to completion, meeting deadlines, interacting with users, and thorough documentation of contributions.

  • Willingness to learn and develop skills in new topics.


Additional Desired Qualifications:

  • Familiar with performance profiling tools (PAPI, HPC Toolkit, Intel Advisor) for understanding and diagnosing performance of applications and kernels on conventional architectures.

  • Experience with higher-level hardware design languages (HDLs) such as CHISEL, PyMTL, or others.

  • Experience with hardware architectural simulators would be beneficial -- either software based such as GEM5 or FPGA-based.

  • Familiarity or experience with software benchmark programs and methods.

  • Knowledge of parallel applications and programming would be a bonus.

  • Experience with FPGA design flows would also be beneficial.

  • Experience using performance analysis tools (e.g. hardware performance counters and code instrumentation frameworks like PAPI or HPCToolkit) will also be beneficial to understand the performance of the complex scientific applications involved in the study. 

  • Experience with parallel computing and/or HPC systems and/or applications.

  • Demonstrated ability to lead technical efforts with teams of people will also be beneficial.


The posting shall remain open until the position is filled.


Notes: 

  • This is a full-time 2 year, postdoctoral appointment with the possibility of renewal based upon satisfactory job performance, continuing availability of funds and ongoing operational needs. You must have less than 3 years paid postdoctoral experience. Salary for Postdoctoral positions depends on years of experience post-degree.

  • This position is represented by a union for collective bargaining purposes.

  • Salary will be predetermined based on postdoctoral step rates.

  • This position may be subject to a background check. Any convictions will be evaluated to determine if they directly relate to the responsibilities and requirements of the position. Having a conviction history will not automatically disqualify an applicant from being considered for employment.

  • Work will be primarily performed at: Lawrence Berkeley National Lab, 1 Cyclotron Road, Berkeley, CA.


Learn About Us:


Berkeley Lab (LBNL) addresses the world’s most urgent scientific challenges by advancing sustainable energy, protecting human health, creating new materials, and revealing the origin and fate of the universe. Founded in 1931, Berkeley Lab’s scientific expertise has been recognized with 13 Nobel prizes. The University of California manages Berkeley Lab for the U.S. Department of Energy’s Office of Science.


Working at Berkeley Lab has many rewards including a competitive compensation program, excellent health and welfare programs, a retirement program that is second to none, and outstanding development opportunities.  To view information about the many rewards that are offered at Berkeley Lab- Click Here.


Equal Employment Opportunity: Berkeley Lab is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, age, or protected veteran status. Berkeley Lab is in compliance with the Pay Transparency Nondiscrimination Provision under 41 CFR 60-1.4.  Click here to view the poster and supplement: "Equal Employment Opportunity is the Law.

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